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Compatibility of Si-gates for Metal-Oxide Dielectrics

IP.com Disclosure Number: IPCOM000007637D
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10

Publishing Venue


Related People

D. C. Gilmer H. Tseng R. I. Hegde C. Hobbs V. Kaushik
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Related Documents

Other References:
1986 - OTHER Oct 2001 - OTHER Vol. 13, No. 9 - OTHER Vol.30 No.12B - OTHER Vol.38 No.10 - OTHER [+more]


Poly-silicon compatibility issues with a metal-oxide dielectric is reported and methods to achieve better Si-gate/metal-oxide compatibility discussed. It can be generally stated that CVD silicon gates using silane (SiH4) deposited at conventional temperatures (620 °C) directly onto HfO2 resulted in films with very high leakage. However, depositing the CVD Si-gate at a lower temperature of 540 °C directly on HfO2 showed about 103 times reduction in gate leakage compared to the conventional 620 °C poly-Si/HfO2 of similar electrical thickness.