Mechanism to Enhance Performance on DRAM DDR Interface by Separating Data Sampling
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10
This proposal describes a mechanism for separating the sampling of positive and negative edge captured data from a FIFO. The important components of this design include a DDR interface. In addition, a receive structure using a FIFO with programmable sample points is needed in the design for this invention. This invention improves performance by optimizing the data sampling.