Browse Prior Art Database

LAYOUT SCAN INSERTION AND SCHEMATIC BACKANNOTATION FOR AT SPEED TEST

IP.com Disclosure Number: IPCOM000007698D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-16

Publishing Venue

Motorola

Related People

Authors:
Tron Womack Fernando Torre

Abstract

A full-scan microprocessor architecture requires connecting every flip-flop in the design together into a serial shill register by daisy chaining the scan data output of one flip-flop (SDO) to the scan data input (SDI) of the next flip-flop. These connections make up the scan chain. At speed testing of such archi- tecture requires efficient connection ofthe scan chains based on the final flip-flop locations, and the ability to reflect or backannotate the scan chain connectivity into the original design schematics for verification.