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Method and Apparatus to Design and Physically Optimize Scan Wrapper for SOC DFT Disclosure Number: IPCOM000007717D
Original Publication Date: 2002-Apr-16
Included in the Prior Art Database: 2002-Apr-16

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Anil Patel Jerome Hannah


Scan chains are traditionally formed in the logical domain to address design for testability concerns, very early in the design flow. Such a design or Intellectual Property (IP) block needs a scan wrapper due to the following reasons; to make multiple scan chains configurable for DFT of System on Chip (SOC) design; to isolate testing of an IP block during testing of the other blocks; to reuse functional vectors for the IP block on a tester for hierarchical AC scan. The wrapper design is generally build according to logical I/O pin order and may use shared I/O scan wrapper cell design. Such kind of traditional scan wrapper design method creates routing congestion due to the fact that the logical I/O pin order may differ with the physical I/O pin order. This method solves the problem of developing scan wrappers for SOC designs, by automatic synthesis and optimization of scan wrapper designs using physical placement information in addition to logical information. As a result it reduces the routing congestion, die size and power consumption of a design, while improving signal integrity and timing performance for both functional operation and AC/DC scan operation.