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A METHOD FOR QUALIFYING INSTRUCTION LINE PREFETCH WITH A LINE-WRAPPED CACHE

IP.com Disclosure Number: IPCOM000007721D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-17

Publishing Venue

Motorola

Related People

Authors:
Ronny L. Arnold Terence M. Potter Paul C. Rossbach

Abstract

In a microprocessor utilizing a memory cache which contains executable instructions, a fetch of an instruction not currently located in the cache can result in idle clock cycles while a load for the instruction is requested from a lower-level cache or memory sub-system. Instruction load requests may be initiated early, as a prefetch load, by assuming an instruction flow such as sequential addresses, thus eliminating some idle clock cycles. There is, though, the problem of requesting a load for a line already held in the cache. If this occurs any lower-level caches and the memory system may be unnecessarily employed, potentially delaying service of data load/store transactions or instruction fetch misses outside the assumed instruction flow. In order to prevent redundant prefetches, it is necessary to ver- ily that a prefetch line is not resident in the cache before the prefetch load request is issued. However, cache utilization will usually preclude expending cache cycles to determine prefetch address residency.