Browse Prior Art Database

STRUCTURES FOR ELECTROMIGRATION RELIABILITY TESTING OF ULSI DEVICES

IP.com Disclosure Number: IPCOM000007751D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-19

Publishing Venue

Motorola

Related People

Authors:
Chii-Chang (Charles) Lee Mark G. Fernandes

Abstract

As the feature size of the ultra large scale inte- gration (ULSI) devices shrinks, the importance of having a reliable via structures increases. Electromi- gration (EM) has been found in the past to be a serious cause of failure in Al interconnect. Many methods were adopted to improve the EM reliabil- ity of the interconnect. Many times, an incorrect test structure leaded the costly experiments to a totally wrong conclusion. The recently published paper(i) is a testament to the problems faced when using improper structures to acquire data. If the data and models are an artifact of the test structure, the design rules generated from such structures result in over design and increased cost of chips. This cost factors into all products and the result is tremen- dous increase in processing cost. lhis is very inefficient.