A 32-BIT STATIC CMOS CARRY-LOOK-AHEAD STRUCTURE OPTIMIZED FOR ENERGY AND PERFORMANCE
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-22
The energy ofa digital CMOS circuit is given by E = 1/2CV2, where C is the loading capacitance being switched and V is the amount ofvoltage swing. By looking at this equation, the best way to reduce the energy consumption is to reduce the voltage swing, due to its squared relationship. For static CMOS, this amounts to the reduction of the supply voltage, since it is expensive to build a circuit with voltage swings less than the supply voltage for large combinational circuits. Limited voltage swings become even more difficult when operating a cir- cuit with a supply voltage close to the threshold voltage ofthe transistors. Additionally, as the supply voltage is reduced toward the threshold voltage of the transistors, the delay through a.gate becomes more sensitive to the gate's transistor stack height due to the body effect of the transistors. Therefore, stack height of a gate can be an important constraint with low voltage design.