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A MULTIBIT SIGMA DELTA ADC ARCHITECTURE

IP.com Disclosure Number: IPCOM000007767D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-22

Publishing Venue

Motorola

Related People

Authors:
Michael R. May

Abstract

Multibit quantizers in sigma delta analog to dig- ital converters increase the achievable SNDR by reducing the quantization noise power by approxi- mately 6dB/bit. However, when a multibit quantizer is used in the feedback loop of a classic sigma delta ADC, the multibit DAC that generates the feedback signal must be very linear. In fact, the linearity of the DAC must exceed the SNDR specification of the entire sigma delta ADC, since nonlinearities in the DAC will show up at the input and degrade per- formance as if the input signal was sampled in a non linear fashion. The linearity requirement on the DAC effectively excludes multi-bit quantizers from generating the feedback signal that is subtracted horn the input signal. Several architectures have been developed to sidestep the DAC linearity requirement while realizing significant performance improvement from the multi-bit quantizer. The most popular is a cascade of modulators, often referred to as a MASH architecture.