Browse Prior Art Database

ACCURATE LOGIC TIMING SIMULATIONS BY PROPAGATING SIGNAL DELAYS AND TRANSITION TIMES

IP.com Disclosure Number: IPCOM000007782D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-23

Publishing Venue

Motorola

Related People

Authors:
Syed A. Aftab Mark R. Rencher Brad Gunter

Abstract

Accurate simulation of delays in logic circuits is normally performed using gate-level context descrip- tions. The delays through each gate is individually analyzed, and propagated from one gate to the next in the signal path. Typical logic simulators can only propagate the logic states (unit delays). However, the delays are ohen strongly dependent on the slope of the input waveform and the output capacitance (loading). For a given set ofprocess (P), voltage (V), temperature (T) and matching (M) conditions and geometry, The output capacitances (in an average sense) are usually extracted in a pre-simulation step. How- ever, input transition time cannot be accurately esti- mated prior to simulation, since it dynamically changes from one gate to the next in the signal path. The delays are thus dependent on the location of the gate in the signal path. This report presents a process to perform accurate delay simulations using standard logic simulators, taking into account the output capacitance loading and the dynamically changing input transition times. Furthermore, sta- tistically accurate delay models can be implemented by taking into account the PvT,M conditions, as well.