PARTITIONING AND ADDRESSING SCAN CHAINS
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-24
As IC's grow more dense in transistor count the time it takes to test those It's also grows. Most designers are looking for ways to reduce the test time while improving the test coverage. One solution is to use a lull scan approach where each and every latch or flip flop is on a serial scan chain that can be written and then read back out. In order to reduce the time required to test the chips this long serial scan chain is usually broken up into many smaller chains and presented to the IC testers in a parallel fashion so that multiple vectors can be presented with every clock. The problem with this approach is that scannable latches and flip flops are larger than their non-scan cousins. This increases the sili- con area used to implement the complete designs. If the area is bigger, then the cost per die is also increased which is something that the designers would like to avoid. Another way to justify the scan logic might be if it could be reused so that another function might also use the chains. This allows the increased area to be amortized over another feature that might add value for the user as opposed to the manufacturer. In the case ofmicroprocessors the extra feature might be On Chip Emulation (OnCE). OnCE is an aid to software engineers debugging their code. It allows them to stop the processor and examine the state of the machine and then change it if required. The entire programmers model must be available for examination and adjustment. The focus ofthis paper is the reuse of the scan chains for OnCE.