POWER ANALYSIS OF CMOS CIRCUITS USING SWITCH-LEVEL SIMULATION
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-24
The subject of low power IC design is ofparticu- lar interest over the last two or three years [I]. Static CMOS circuits are very suitable for this purpose since they do not consume power in the stationary state. The goal of the research reported in this paper was to develop a fast and accurate method for power estimation of CMOS circuits which can be used in algorithms that optimize CMOS designs.