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Method for an optimized 10-GHz differential signaling package layout for a JCI (thin) substrate flip-chip package with FR-4 board stackup

IP.com Disclosure Number: IPCOM000007825D
Publication Date: 2002-Apr-25

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an optimized 10-GHz differential signaling package layout for a joint communications instruction (JCI, thin) flip-chip ball grid array (FCBGA) package with FR-4 board stackup. Benefits include improved performance and improved reliability.