ENHANCED DRAIN FORMATION FOR 1.5T FLASH
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-Apr-30
A new drain region process to control erased V, distribution by moving drain junction implants after the ON0 formation has been proposed for a 16-bit microcontroller with embedded flash EEPROM memory. The new integration reduces drain implant mask alignment sensitivity and improves the proc- ess to be forgiving and manufacturable. This improve- ment is believed to carry the current 0.65 pm flash technology into next generation of 0.55 ,um regime and beyond.