Browse Prior Art Database

# 2 TO 9 MODE PIN DECODER FOR FPGA's

IP.com Disclosure Number: IPCOM000007955D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-May-08
Document File: 2 page(s) / 102K

Motorola

## Related People

Authors:
Dandas Tang Michael Shieh

## Abstract

Design of a Mode Pin Decoder is proposed to decode 9 output functions by using only two input pins. A conventional decoder would have required 4 pins to implement 9 output functions. Thus with the present invention, 2 package pins will be saved for other usages. The invention shown in Figure 1 can be understood by examining the following 9 cases: "01' N48 & N135 are on, X2 = "1:' X4 = "II' A = "1:' AB = "0:' AZB = "1;' X9 = "0: X10 = "1; Xl1 = "1;' B = "1:' BB = "0: BZB = "1;' Then, P89, P159 & Pl60 are onout = "1;' and the rest of the outputs are "0: CASE E: CASE A: model = "0: mode2 = "0:' out1 = "1" Xl, X3 are "0; P59 & P145 are on, X5 & X7 = "01' N48 & Nl35 are on, X2 & X4 = "01' A = "0:' AB = "1:' AZB = "1:' X9 = "0; X10 = "1;' X11 zz "1:' B = "0:' BB = "1:' BZB = "II' Then, P89, P153 & P154 are'on, out1 = "1" and the rest ofthe outputs are "01' model = "0:' mode2 = "Z:' out5 = "1" Mode2 = "Z: X3 = Vpp (-6.5v), P147 is on, W2 is a voltage divider, inverter (1151) is properly sized to convert the voltage level of X7 (-2 volts) to "0" at X8, N135 turns 06 X4 = "II' Xl = "0:' P59 is on, X5 = "Of' N48 is on, X'j = "Of' A = "0:' AB = "1:' &B = "1:' X9 = "1;' Xl,, = "0; Xl 1 = "1;' B = "1:' BB = "0: BZB = "01' Then, Pl65, P162 & P161 are on, out5 = "1:' and the rest of the outputs are " >> 0.