Browse Prior Art Database

SPECIAL ADHOC TEST MODE FOR FUNDAMENTAL CACHE SPEED PATH

IP.com Disclosure Number: IPCOM000007970D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-09

Publishing Venue

Motorola

Related People

Authors:
Joseph C. Circello Anup S. Tirumala

Abstract

In many microprocessors (MPU) with on-chip memories, the cache read path defines a critical speed path. This speed path is shown in the figure, a block diagram of a 2-way, set-associative cache. The path typically begins with the cache address register accessing the tag (also known as the direc- tory) arrays. The tag outputs are compared to the upper address bits to determine if the access "hits" in the cache. The raw hit signals are then combined to form the mux select to gate the appropriate data back to the processor core. Additionally, the raw hit signals form a transfer acknowledge (TA) signal to terminate the cache access in the event of a hit. Finally, the processor core uses the transfer acknowledge signal to form a clock enable signal to load the cache read data into the destination reg- ister. Thus, there are typically two distinct timing arcs of interest: first, the cache transfer acknowl- edge signal factoring into the clock enable for the destination register in the processor core, and sec- ond, the actual cache read data. These paths often are the frequency limiting speed paths for the microprocessor.