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TESTABLE MULTIPLIER ARRAY DESIGN IN THE FLOATING POINT OF MICROPROCESSORS

IP.com Disclosure Number: IPCOM000007998D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-10

Publishing Venue

Motorola

Related People

Authors:
Romesh M. Jessani Kofi Vida-Torku Craig Hunter

Abstract

Multiplier arrays are designed as regular itera- tive arrays which include Booth encoders, Booth muxes and carry save adders' (CSA). Uncontrolled constants feeding into the multiplier array results in untestable circuits within the Booth mux and CSA circuits. This invention provides a high test cover- age for multiplier arrays.