AN ALGORITHM FOR INSTRUCTION CACHE ARBITRATION AMONG MULTIPLE INSTRUCTION STREAMS
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-10
In processor designs utilizing branch prediction, imperfect branch prediction accuracy leads to per- formance degradation. The severity of the perfor- mance degradation depends on the prediction accu- racy and the penalty per misprediction. This paper presents an approach which focuses on reducing the penalty per misprediction to enhance processor per- formance.