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AN ALGORITHM FOR INSTRUCTION CACHE ARBITRATION AMONG MULTIPLE INSTRUCTION STREAMS

IP.com Disclosure Number: IPCOM000007999D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-10
Document File: 4 page(s) / 198K

Publishing Venue

Motorola

Related People

Authors:
Ralph McGarity Terence Potter Tom Thomas

Abstract

In processor designs utilizing branch prediction, imperfect branch prediction accuracy leads to per- formance degradation. The severity of the perfor- mance degradation depends on the prediction accu- racy and the penalty per misprediction. This paper presents an approach which focuses on reducing the penalty per misprediction to enhance processor per- formance.