LOW DROP OUT REGULATOR WITH NMOS OUTPUT
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-14
The proposed circuit is shown in Figure 1. The intent of this circuit is to provide a regulated volt- age that is insensitive to supply voltage, tempera- ture and processing. The other intent is to supply a regulated voltage that remains within specification as the supply voltage comes near to the regulated voltage.