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FLEA: FANOUT AND LOAD ESTIMATOR APPLICATION

IP.com Disclosure Number: IPCOM000008113D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-20

Publishing Venue

Motorola

Related People

Authors:
Jeff L. Freeman

Abstract

Typically, logic synthesis of chips is done in a piecemeal approach, since the current technology uses too much computer resources for design bier- archies of 50,000 gates or more (logic synthesis takes days to complete). By breaking up a design hierarchy into smaller logic synthesis runs, the throughput is much more manageable. However, this requires the designer to supply time budget constraints as well as fanout and load information for signals going to and from the sub-design of the chip hierarchy. Tbis disclosure presents a tool that can address the fanout and load information requirement.