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Method for a high-performance DRAM address mapping mechanism Disclosure Number: IPCOM000008164D
Publication Date: 2002-May-22
Document File: 3 page(s) / 60K

Publishing Venue

The Prior Art Database


Disclosed is a method for a high performance DRAM address mapping mechanism. Benefits include improved performance.

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Method for a high-performance DRAM address mapping mechanism

Disclosed is a method for a high performance DRAM address mapping mechanism. Benefits include improved performance.


              Mapping physical addresses when selecting DRAM devices and banks can be done in many ways. The higher performance schemes provide a better (even) distribution of addresses across devices and banks as compared to the lower performance schemes. They may skew the addresses across only a small number of banks and may result in many page misses. Low performance is typically a result of a large number of page misses. Extracting the best memory system performance is critical for next-generation processors. Selection of a high-performance mapping scheme is an important contributor toward this goal.

              In linear address mapping (see Figure 1), the bank selection bits are typically adjacent to the page selection bits. The row selection bits are next to the bank selection bits. The rank selection bit follows the highest row selection bit. This simple address-mapping scheme is commonly implemented in conventional chipsets.

              In shuffled address mapping, rank and bank selection bits are shuffled in the address map (see Figure 2), where lower order bits specify a device rank and a bank. This mapping does not require any extra hardware. The shuffling is performed with the goal of capturing adequate spatial locality and avoiding page conflicts   resulting from write back of cache lines. By shuffling selection bits appropriately, this scheme has the potential to provide higher performance than the linear address map.

General description

              The disclosed method includes an address mapping technique that can be implemented in a chipset to provide consistently high performance across a large number of benchmarks. The bank and rank selection bits are generated by an exclusive-or function on a set of specified bits. This algorithm is used for any type of memory device when the following criteria are met:

·        The resultant scheme consistently provides a high level of performance across memory device organizations, across benchmarks, and across different virtual to physical page mappings done by the operating system.

·        The selection support the ease of future expansion of the memory system as memory device technology improves.


              The disclosed method provides advantages, including:

·        Evenly scattered addresses across banks and devices, lowering page misses

·        Improved hashing property for scattering addresses

·        Improved chipset performance

Detailed description

              The disclosed method generates bank and rank selection bits as an exclusive-or of specified bits from the address map. Unlike the other schemes, this method requires the use...