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Method for a PCI/PCI-X device data prefetcher Disclosure Number: IPCOM000008166D
Publication Date: 2002-May-22
Document File: 5 page(s) / 131K

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The Prior Art Database


Disclosed is a method for a PCI/PCI-X device data prefetcher. Benefits include improved performance.

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Method for a PCI/PCI-X device data prefetcher

Disclosed is a method for a PCI/PCI-X device data prefetcher. Benefits include improved performance.


              Conventionally, the transmit performance of gigabit Ethernet devices is limited by a number of factors within the system. One is the latency of reads to system memory.

              To transmit data onto a network, conventional Ethernet devices follow a very simple procedure:

1.      Get a list of data to send

2.      Get each piece of data in the list

3.      Send the data

4.      Repeat

              This sequence can be performed many thousands of times per second. The device driver creates this list of tasks in memory and notifies the device when it is ready.

              Conventional networking devices reside on the PCI or PCI-X bus of a system. Data to be transmitted is given to the device driver by the operating system. The driver creates and maintains a ring of descriptors in system memory. Each descriptor contains the location and length of a fragment of data to be sent. The driver signals the PCI device to read the descriptors.

              To reach main memory on a shipping server platform, data must cross a PCI bus, a hub-link bus, and a memory bus (see Figure 1). The PCI device begins by initiating a read on the PCI bus.

This read is claimed by the PCI bridge that begins a read on the hub-link bus. The memory controller hub (or MCH) in the system begins fetching the data from system memory. When the data is retrieved, it is sent back down the hub link to the PCI bridge that completes the delivery of the data to the PCI device.

              The network controller has a list of buffers that must be transmitted and their lengths. One by one, the device issues read commands on the PCI bus to get these buffers out of system memory. These reads follow the same path through the system as the descriptor reads did. As each piece of data is returned, it is sent out onto the network.

              The data is delayed by every bus or bridge that must be crossed. The total delay from descriptor read to packet transmission can be computed (see Figure 2).

              This process is illustrated in a process diagram (see Figure 3). The four blocks in the diagram are the four system components involved in packet transmission.


General description

              The disclosed method is PCI/PCI-X device data prefetcher. A script of upcoming reads is transferred over the bus in the form of descriptors. A bridge predicts the memory reads that are about to be issued and prefetches the data so that it is waiting in the bridge’s buffers or...