IMPLEMENTATION OF A LOW-SKEW CLOCK DIVIDER CIRCUIT FOR LOW-POWER APPLICATIONS
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-24
Traditional clock-divider circuits use a flip-flop following the path through the flip-flop, any skew and then a buffer to drive the output of the divider generated is simply associated with the tristate buffer. circuit. However, in wireless and other low-power applications, the clock-to-output delay on a flip-flop The figure below shows an example circuit. in the chosen library may result in clock skew Each flip-flop, with the inverting input, could between the source clock and the divided clock. constitute a clock divider circuit. Note that this This paper describes an alternative circuit to circuit includes an additional inverter and two generate a divided clock with much less skew. tristate buffers. The inverter that negates clock-in causes one flip-flop to operate exactly out-of-phase The theory behind this circuit is to use the input with the other. Thus, clka changes on the fall clock to enable a tristate buffer to drive an aheady- of clock-in, whereas clkb changes on the rise of setup value on the clock wire. Thus rather than skew clock-in.