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AN ARRAY BUS ARCHITECTURE FOR MEMORIES

IP.com Disclosure Number: IPCOM000008195D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-27

Publishing Venue

Motorola

Related People

Authors:
John Dunn Theo Freund Joseph Harris

Abstract

A unique RAM implementation has been developed which uses an Array Bus architecture. In this structure one or more partitioned RAM blocks is controlled by a common Control Section. In the following the architecture, motivating factors, and implementation of the architecture will be discussed.