Browse Prior Art Database

FULLY TESTABLE TRISTATE MULTIPLEXER FOR CIRCUITS WITH TIED DATA INPUTS

IP.com Disclosure Number: IPCOM000008215D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-28

Publishing Venue

Motorola

Related People

Authors:
Mike Snyder Rajesh Raina Marvin Denman

Abstract

Multiplexers (mux) implemented using pass- gates are inherently challenging to test'. A weak pull-down device at the output (a.k.a. test pulldown) provides a test solution in a limited number of usage situations'. In this paper we describe a frequently occuring usage situation for pass-gate muxes-tied data inputs-for which the test pulldown solution fails to provide complete testability. We propose our invention-a pass-gate mux circuit-that is completely testable in the presence of tied data inputs. We show that the proposed circuit is better than alternate solutions in terms of area overhead, functional delay and design time overhead.