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A Method for Suppressing Parasitic Bipolar Effects in Partially-Depleted and Fully-Depleted SOI-CMOS SRAM Arrays Through the Utilization of a False-Write Strategy

IP.com Disclosure Number: IPCOM000008304D
Publication Date: 2002-Jun-04

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method which uses a high frequency bitline voltage-pulse (e.g. false-write) that occurs at a fixed period of time between read and write accesses to the memory array. The time and frequency of false-write can be tailored to a specific cache size or operational specification. Benefits include the potential to increase high-performance/high-margin chip yield.