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Disclosed is a method for a framed structure for the efficient probing of a digital signal processing (DSP) based transceiver. Benefits include improved performance and improved ease of design.
English (United States)
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This is the abbreviated version, containing approximately
62% of the total text.
Method for a framed structure for the efficient probing of
a DSP-based transceiver
Disclosed is a method for a framed structure for the efficient
probing of a digital signal processing (DSP) based transceiver. Benefits
include improved performance and improved ease of design.
DSP-based transceiver designs, on-chip data-path signal probing is required to
validate the design of the system as well as the implementation. Because these
digital signals (words) contain many bits, many digital I/O pins are required
to output the signal from the chip. I/O pin availability becomes an issue. In
some applications, the number of the digital I/O pins may be so limited that
the probing of internal signals becomes impossible.
disclosed method includes a framed structure for probing a DSP-based
method contains the following components:
High-rate synchronous clock
On-chip parallel-to-serial (P/S) converter
Off-chip serial-to-parallel (S/P) converter
Digital-to-analog (D/A) converter
P/S converter changes the bussed signal (word) into serial format using a
high-rate synchronous clock (see Figure 1). The serialized signal is framed
then sent off the chip along with the synchronous clock. Using this procedure,
only two I/O pins are required. When the signal is received off-chip, a frame
detector is applied to resynchronize the data. An S/P converter recovers the