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METHOD AND APPARATUS TO HIDE MEMORY LATENCY

IP.com Disclosure Number: IPCOM000008345D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-07

Publishing Venue

Motorola

Related People

Authors:
Bryan Marietta C.S. Hui Jikku Venkatramani Hai Bui

Abstract

An in-line cache is a cache that is logically between the processor and the system bus. It is used to improve system to processor bandwidth by caching data and allowing increased interface frequency, while reducing system bus bandwidth requirements. If there is a cache miss at the in-line cache a memory system read operation is required. This read operation has a long latency which ties up the processor to in-line cache bus in a pipelined system. It is desirable to use this latency period for other bus operations without terminating the memory read. The PowerPC 60X bus architecture is assumed in this paper.