A METHOD FOR A MULTI-TIME-SLOT LEVELIZED COMPILED HARDWARE SIMULATOR
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-10
On the 68060 design, we had about 2 million vectors to run against the hardware model of the chip. It would take more than three weeks to do this using the Verilog-XL simulator from Cadence because at the time, the Verilog simulation was about 0.4 Hz. Fewer verification cycles lead to lower confidence in a correct design. Mask shop was delayed many months because design errors came up so late in the design process. Even after first silicon, functional design errors were found which led to many more mask revisions of the 68040.