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Method for a programmable fractional multiplier PLL clock generation

IP.com Disclosure Number: IPCOM000008415D
Publication Date: 2002-Jun-12
Document File: 3 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a programmable fractional multiplier phased-lock loop (PLL) clock generation. Benefits include improved performance.