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Method for a Switch-on-Event Multithreading algorithm using micro-code emulation in Instruction Set Architecture with dual processors

IP.com Disclosure Number: IPCOM000008416D
Publication Date: 2002-Jun-12

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a Switch-on-Event Multithreading (SoEMT) algorithm using micro-code emulation in Instruction Set Architecture (ISA) with dual processors. Benefits include improved performance.