MAINTAINING STABLE PLL PARAMETERS
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14
Maintaining stable Phase Lock Loop (PLL) parameters (e.g. jitter and peaking) is a key goal in PLL based clock driver designs. Unfortunately, in typical clock driver designs the PLL parameters become unstable when the bandwidth of the PLL, Kpll, nears either the zero or pole of the loop filter (~2 and ~3, respectively). This paper focuses on a method of keeping PLL parameters stable by using an electronically adjustable loop filter to optimize the distance between ~2, ~3, and Kpll. The theories and equations presented are referenced from the book by Dan Wolaver, "Phase-Locked Loop Circuit Design".