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Browse Prior Art Database

MECHANISM FOR GENERATING COUNTED HARDWARE BREAKPOINTS UTILIZING AN EXTERNAL CPU PIPELINE MODEL

IP.com Disclosure Number: IPCOM000008446D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14

Publishing Venue

Motorola

Related People

Authors:
Alex Iles

Abstract

Microprocessor/microcontroller ln-circuit- Emulator (ICE) systems typically provide a hard- ware breakpoint mechanism in order to halt CPU operation to allow the user to perform intrusive interaction with their application. The CPU may be stopped in response to a user command or to detection of a specified system event.