MECHANISM FOR GENERATING COUNTED HARDWARE BREAKPOINTS UTILIZING AN EXTERNAL CPU PIPELINE MODEL
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14
Microprocessor/microcontroller ln-circuit- Emulator (ICE) systems typically provide a hard- ware breakpoint mechanism in order to halt CPU operation to allow the user to perform intrusive interaction with their application. The CPU may be stopped in response to a user command or to detection of a specified system event.