THUNDERBOLT BUFFERED DRIVER CONTROLLER DESIGN
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-19
This circuit arbitrates video display memory access between a low power Motorola micro- controller running at parity speed with the display (about 800K Hz) and the display refresh mecha- nism. Because of the displays need to be constantly refreshed, and the low speed of the processor, it is virtually impossible to guarantee access to the video memory for data refresh. This mechanism would permit such access without increasing clock speed or putting the micro-controller into wait states which might cause it to miss a service interrupt such as a page or other real time radio service request. At the same time, this design works equally well with a conventional low-cost SRAM.