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Disclosed is a method for a lower power multiplier array mirror-CPL carry-save compressor. Benefits include improved functionality, improved performance, and improved power performance.
English (United States)
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Method for a lower power multiplier array mirror-CPL
Disclosed is a method for a lower power multiplier array
mirror-CPL carry-save compressor. Benefits include improved functionality,
improved performance, and improved power performance.
method is a carry save adder (CSA) comprised of pass transistors (n-transistors),
p-transistors used as cross-coupled devices, and a combination of n-
and p- transistors used on the mirror logic and inverters. The CSA compresses
3 bits into a 2-bit number represented as the sum and carry of all three
individual bits. The sum processing is implemented with CPL logic (see Figure
1), while the carry processing is implemented with mirror logic (see Figure 2).
This new CSA implementation
combines the CPL and mirror circuit implementation techniques (see Figure 3).
This combination of designs enables the application to take advantage of each
logic-implementation technique, producing an optimal design.
method provides advantages, including:
Improved functionality due to the implementation of the sum and carry