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MOTOROLA Technical Developments
TRANSISTOR THERMAL IMPROVEMENT
by Philippe Dupuy and Thierry Sicard
ABSTRACT
With the shrink path of new SmartMOS tech-
nologies, the factor Ron.Area always decreases with each process generation. So for a given Ron, the area becomes smaller; this results in a new problem of energy capability. As the energy is proportional to the area for an energy pulse given, when the area decreases the energy capability decreases too. Due to this problem, the shrink of the power component is limited.
STATEMENT OF THE PROBLEM
If we want to achieve a Ron parameter, the new technology will give an area too small to sustain the energy capability needed by power application. This problem is compounded for an inductive load. So the challenge is to improve the area efficiency of power structures to have a better use of the silicon to sustain the energy without increasing the area too much.
SOLUTION
The solution presented here is not a general solution for the above problem. The idea is only applicable when we have two transistors which do not work in the same time. (The best examples are the full and half bridge configuration.) So the main idea is to SHARE the area between 2 transistors which are active one after another. Figure I shows a thermal simulation between three different cases to compare the advantage of the solution proposed.
First of all, in the three cases the same energy
pulses have been used (5OW.lmS = 50mJ).
Case I : Case I is the reference simulation repre- senting the standard application. In this case the energy pulse is injected in an area of 0.5mm'. The curve named "Case 1" in Figure I represents the temperature reached after the pulse in the middle of the transistor,
Case 2: Case 2 is a second reference simulation representing the standard application. In this case the energy pulse is injected in an area of lmm'(two times bigger than in Case 1). The curve named "Case 2" in Figure I represents the temperature reached after the pulse in the middle of the transistor. We noted th...
