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Disclosed is a method for generating on-chip scan clocks from a slow scan clock control signal without a clock tree. Benefits include an improved test environment.
English (United States)
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Method for generating on-chip
scan clocks from a slow scan clock control signal without a clock tree
Disclosed is a method for generating
on-chip scan clocks from a slow scan clock control signal without a clock tree.
Benefits include an improved test environment.
In automated test pattern
generation (ATPG) testing, the tester must control the functional and scan
clocks of the device under test (DUT). The tester must also have access to the
DUT scan chains. One type of scan methodology requires a pair of nonoverlapping
clock signals applied in sequence to shift the data from one scan cell to
I/O pin, Scan_CLK_CNTL, controlled by automated test equipment (ATE), uses a
pulse signal to generate a pair of nonclock lapping clocks, ACLK and BCLK (see
Figure 1). The rising edge of SCAN_CLK_CNTL triggers the rising edge of ACLK
and the falling edge of SCAN_CLK_CNTL triggers the rising edge of BCLK. The
edge placement accuracy is not required to be as high as the core clock because
the signal must pass a pair of back-to-back flip-flops before it enters the
clock generator LTCC to eliminate the metastability problem. After that, the
SCAN_CLK_CNTL becomes a data signal synchronized with MCLK.
III is a copy of signal I with a 2-MCLK latency, and signal I is a copy of
SCAN_CLK_CNTL with a 1-MCLK latency (see Figure 1). Performing an AND operation
on signal-I and the inversion of signal III produces ACLK. Similarly,
performing an AND operation on signal III...