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SYNTHESIS METHODOLOGY FOR LOW POWER STANDARD CELL DESIGNS

IP.com Disclosure Number: IPCOM000008699D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-03
Document File: 2 page(s) / 79K

Publishing Venue

Motorola

Related People

Authors:
Daniel Cronin Rick Fernandez

Abstract

In CMOS systems, there are generally two devices are "on" during an input transition. In major components of current drain. The first is the order to achieve a low power design both of these current required to charge the capacitive nodes components must be monitored and controlled within the system, and the second is the short- during logic synthesis. circuit current that occurs when both the P and N 1% * * Fig. 1 Charging Model The power dissipation resulting from the charging current is a direct function of the load capacitance, specifically P=C*V'*f, while the short-circuit current is a function of I*V, where I is the mean short circuit current. This current, I, is a function of the input and output slew rate as well as the equivalent resistance of the MOSFET devices in the short- circuit path from Vdd to Vss (Figure I). Therefore, in order to control the power within a design both the charging current and short-circuit current must be monitored and optimized accordingly.