CIRCUIT OF PREVENTING COUPLING NOISE AND NOISE SPIKE FROM COMING INTO CIRCUIT
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-04
Cache memory usually partitions into subarrays which are selected into group to make double words (64 bits), quad words (128 bits) or more (in the future) so data out of each subarray usually wired-or the same bus with the other subarrays (before going to final stage as data driven out of cache) and this common bus is dynamic and very long. In the future microprocessor if the dynamic bus is too crowded and spacing between bus line has to be kept in minimum due to area restriction, the coupling noise can exist between bus lines. The coupling voltage exist at the middle line when precharge goes High and supposed the weak feedback P-device (Figure 1) to keep data at High but if the two adjacent lines are Low they will cause coupling voltage to drop off voltage of the middle significantly and if there is a large voltage drop off enough, it will cause a false data at the final stage. In future the process tend to increase coupling noise.