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A Power-Saving Mechanism for a DMA Address Bus Disclosure Number: IPCOM000008766D
Original Publication Date: 2002-Jul-10
Included in the Prior Art Database: 2002-Jul-10

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Eytan Hartung Vasan Venkataraman


A typical DMA controller operates under the control of a microprocessor. The microprocessor instructs the DMA controller to transfer a block of data from consecutive locations in memory to consecutive locations in another region of the memory space. The microprocessor provides the DMA controller the source and destination starting addresses and the number of words to be transferred. The DMA controller maintains the address pointers as well as a word counter. Existing DMA controllers begin at the provided starting address and access the memory locations in numerical order. This article describes a mechanism that saves up to 50% of the address current-drain by utilizing a dynamically adjustable counter that for an address bus width of m will address the n lowest significant bits in Gray code sequence while counting the upper m-n bits in binary code. The dynamically adjustable selection of n maximizes the benefit for any buffer size and location. Also - it transfers the data in a Gray code sequence, but preserves the original data order once it is stored in memory, a requirement for DMA transfers. Therefore This mechanism is not limited in term of subsequent accesses to the stored data must be transferred as entire block, and thereby not limiting the application to fixed size blocks.