Browse Prior Art Database

A Method for Barrier Seed Integration for ULSI Copper Metallization

IP.com Disclosure Number: IPCOM000008807D
Original Publication Date: 2002-Jul-15
Included in the Prior Art Database: 2002-Jul-15

Publishing Venue

Motorola

Related People

Inventors:
Rajesh A. Rao Muralidhar Ramachandran Bich-Yen Nguyen

Abstract

A method for barrier-seed integration for the fabrication of Cu interconnect lines in high aspect ratio trenches and vias in the bank end of the line (BEOL) of typical IC processing is described. Conformal coverage of the thin barrier layer and Cu seed in such deep trenches and vias continues to be a challenge. The method described consists of using Atomic Layer Chemical Vapor Deposition (ALCVD) to deposit the barrier metal (typically Ta or TaN or a bilayer Ta/TaN) and a very thin layer of a catalyst metal such as Pt, Sn, Pd or Cu. This is followed with an electroless plating step during which the catalyst metal deposited in the previous step serves as an activation layer for electroless deposition of the Cu seed. Once a sufficiently thick Cu seed is deposited, the vias and trenches are filled with Cu in an electroplating process. This integration scheme eliminates the need for a physical vapor deposition step, which is the primary cause for step coverage related failures in BEOL interconnects.