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METHOD OF IMPROVING CONTACT ETCH MARGIN BY REDUCING OXIDE THICKNESS IN N+ DOPED CONTACTS USING N+ IMPLANT EXCLUSION MASK

IP.com Disclosure Number: IPCOM000008831D
Original Publication Date: 1998-Sep-01
Included in the Prior Art Database: 2002-Jul-17

Publishing Venue

Motorola

Related People

Authors:
Kevin Cox Craig Gunderson Norm Herr

Abstract

A technique for defining an implant mask which can improve process margin for the poly 2 to N+ con- tact etch for CMOS or BiCMOS processes that com- bine post-N+ implant oxidizing anneals with self- aligned poly 2 to N+ contacts and silicon dioxide gate capping layers. By careful exclusion of the N+ implant from the poly2 to N+ contact area the thick- ness of thermal oxide in the N+ regions is reduced by elimination of dopant enhanced oxidation in those areas. regions is as much as 5 times lower than the etch rate of the gate cap oxide. Minimizing the oxide thickness in N+ to poly 2 contact regions adds process controlla- bility.