Enhancing SPI protocol to enable Asynchronous Master or Slave transfer request.
Original Publication Date: 2002-Jul-17
Included in the Prior Art Database: 2002-Jul-17
The SPI interface Synchronous Peripheral Interface is a high speed, low latency, low pin count, used for communicating from microprocessors to simple peripheral components in embedded systems. The HW simplicity of the SPI interface has led to its successful deployment. SPI is based on a simple Master/Slave relationship and defined frame structures that does not adequately address Network layer where for the Slave device to establish and terminate network communications. The additional functions are needed to facilitate products where slave devices provide a higher level of functionally. These functions can simply be implemented with low SW overhead utilizing the CSPI HW on the Motorola DragonBall MX1 processor.