Parity Implementation for Dual-Flash EEPROM Microcontroller
Original Publication Date: 2002-Jul-17
Included in the Prior Art Database: 2002-Jul-17
Parity checking is required on a microcontroller with a large embedded flash eeprom memory unit. Since the data in a re-writable memory unit, the parity information must also be in a re-writable unit. This invention is intended to provide the most area and test time efficient implementation for the data and parity, given the large flash eeprom memory required.