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Browse Prior Art Database

Parity Implementation for Dual-Flash EEPROM Microcontroller

IP.com Disclosure Number: IPCOM000008837D
Original Publication Date: 2002-Jul-17
Included in the Prior Art Database: 2002-Jul-17
Document File: 2 page(s) / 14K

Publishing Venue


Related People

Mark Weidner Jason Perez Joe Jelemensky


Parity checking is required on a microcontroller with a large embedded flash eeprom memory unit. Since the data in a re-writable memory unit, the parity information must also be in a re-writable unit. This invention is intended to provide the most area and test time efficient implementation for the data and parity, given the large flash eeprom memory required.