Method for low stress, high yield plated-through-hole designs in metal core flip-chip microelectronic packages

Method for low stress, high yield plated-through-hole designs in metal core flip-chip microelectronic packages

Disclosed is a method for low stress, high yield plated-through-hole (PTH) designs in metal core flip-chip microelectronic packages. Benefits include improved reliability.

Background

              Flip-chip packages using metal cores tend to have PTH-to-dielectric material shoulder cracking and via failures associated with coefficient of thermal expansion (CTE) mismatch in thermal cycling. The conventional method for creating through holes in metal core packages is through mechanical or laser drilling and/or chemical etching. The PTHs have sharp edges (see Figure 1) that are subject to dielectric and via cracking as a result of stress (see Figure 2).

Description

              The disclosed method is a PTH design for metal core flip-chip packages. The key elements are:

·        Flip-chip microelectronic packages

·        Plated through hole design

              The disclosed method utilizes a chamfer or rounding-step post metal core through hole to impart a smooth transition and reduced-stress area within the core to PTH regions (see Figure 3). With rounded edges, dielectric cracking is reduced (see Figure 4).

Advantages

              The disclosed method provides advantages, including:

·        Improved reliability due to reduced residual stress tensors at the edges

·        Improved reliability due to reduced potential for crack creation/propagation due to high stress concentrations at the sharp edges