Publishing Venue
The IP.com Prior Art Database
Abstract
Disclosed is a method for process performance state-transition tables. Benefits include improved functionality and improved performance.
Method for process performance state-transition tables
Disclosed is a method for process performance state-transition
tables. Benefits include improved functionality and improved performance.
Background
In
a conventional processor system, many different techniques for generating the
multiple operating clock frequencies are used. For example, the root clock
frequency, which might be used for the processor core, may be generated by a
phase-locked loop (PLL). Other related frequencies, such as the memory bus
frequency, may be derived from the PLL frequency by a clock divisor.
Alternatively, the processor core clock frequency may also be generated by
dividing the PLL frequency instead of taking it directly from the PLL.
Furthermore, different performance costs are associated with changing these
various frequencies. For example, changing the core PLL frequency may take a
relatively long time because the PLL must synchronize, during which the
processor and other subsystems driven by the PLL cannot be active. Alternatively,
switching the clock divisor would take comparatively little time (restricting
the range of allowable frequencies) and enables all subsystems to remain
operational.
Conventionally,
not many systems present a range of operating frequencies. However, as
processors become increasingly powerful and complex, the number of states and
requirements for power efficiency will increase. For example, some network
processors currently enable five core PLL frequencies with two different
dividers for other operational frequencies.
Description
The
disclosed method specifies the available states and transitions in a processor
system capable of multiple operating frequencies and/or voltages. The firmware
of a processor system can present data to the operating system representing the
available configurations for a particular hardware instantiation. For example,
a system that can operate at multiple processor-clock frequencies could provide
a state table correlating different clock frequencies with the power
consumption at each frequency. The table could contain values that indicate the
available transitions between states (clock frequency configurations). The
method includes a technique for specifying the characteristics (for example,
latency) of transitions between different table rows (processor frequencies) in
a clear and concise representation.
The
disclosed method assigns a group-ID to each row in the processor frequency
configuration table. Transitions between rows with the same group-ID correspond
to low-latency transitions. They do not require an expensive transition , such
as might be caused by a PLL re-synchronization. On the other hand, transitions
between rows with different group-IDs do require an expensive transition. and therefore would incur
significant processing delay. This technique is a simple way to represent the
transitions between different states without requiring a full table
specification that specifies the transition from...