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IDEAL LEAD FRAME (IDL) FOR THE BUMP CHIP CARRIER (BCC) USING THE VARIABLE/INCREMENTAL SUBSTRATE NESTING (VISN) METHODOLOGY

IP.com Disclosure Number: IPCOM000009038D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Aug-02

Publishing Venue

Motorola

Related People

Authors:
Pat Crawford Dwight Daniels Jeffrey Alan Miks Dilip Pate1

Abstract

The Ideal Lead Frame (IDL) for the Bump Chip Carrier (BCC) using the Variable/Incremental Substrate Nesting (VISN) methodology provides a single leadframe design that can be used for many different combinations of I/O pin counts and pack- age sizes. This approach accepts a wide range of die sizes on a single design (including rectangular die and varying aspect ratios). It also allows wire bond- ing location flexibility, and can shorten wire lengths for improved electrical performance, which reduces wire sweep. Overall improvements of the 'one-size- fits-all' lead frame are simplified inventory manage- ment; which can result in reduced cost, and reduced cycletime for this approach.