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A THERMALLY ENHANCED 2-LAYER PBGA SUBSTRATE DESIGN

IP.com Disclosure Number: IPCOM000009041D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Aug-02

Publishing Venue

Motorola

Related People

Authors:
L. Michael Eyman Zane Johnson

Abstract

For typical plastic ball grid array (PBGA) pack- ages, 90% of die power dissipation is conducted downward, through the package substrate, into the printed wiring board. Unfortunately, two-layer PBGA substrates often lack sufficient copper cover- age and trace orientation to effectively spread power generated by the die. As a result, thermal perfor- mance suffers.