ENHANCED INTERRUPT CAPACITY IN A QUEUE INTERFACE
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-07
This proposal relates to a Queued Serial Parallel Interface (QSPI) which is used in connection with Micro Controller Units (MC&). The figure illus- trates a QSPI with a RAM (Control and Data RAM), a control block, a queue pointer, and a buffer/shift register. Using the pointer and the control block, the register transfers queue data from the data RAM to a serial output.