EEPROM RELIABILITY PREDICTION SCREEN USING VARIABLE BITLINE VOLTAGE IN BULK PROGRAM MODE
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-09
Testing NVM arrays is very time consuming and costly, especially when trying to eliminate weak devices which could become early life failures. This prediction screen will identify potential unreliable bits in the EEPROM array in a time effective and cost effective maturer. The screen uses a combination of on-chip hardware and external tester control utilizing real time analysis of Vt distributions and including a novel binning algorithm to each die under test.