METHOD AND ALGORITHM FOR FAST PARALLEL PROGRAMMING OF FLASH EEPROM
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-12
Flash EEPROM arrays are growing in array size with linear scalingof test time. A flash array has control registers associated for programingand eras- ing, and an external program/erase voltage pin. A flash array requires a program algorithm using these registers. For multiple flash arrays on a chip, the program algorithm has to be repeated for each dif- ferent array and control register locations, thus increasing software time during test. Also mutiple voltage pins are required unless the pin current can be controlled to provide enough current for each flash array.